The present invention relates to a liquid-crystal display apparatus, in which one frame is divided into N frames, and an identical scanning electrode is selected for every 1/N field to be driven.
In recent years, dot-matrix type liquid-crystal display panels have tended to have larger screens, and the number of scanning lines therefore has increased accordingly. However, as the number of scanning lines increases, a duty ratio also increases and contrast is impaired. As shown in FIG. 1, a liquid-crystal panel is vertically divided into two portions, and upper and lower screens are simultaneously driven to reduce the duty ratio. FIG. 2 shows an arrangement of a liquid-crystal television system adopting the vertically divided liquid-crystal display panel. Referring to FIG. 2, reference numeral 21 denotes an antenna; and 22, a receiver including a tuner, an intermediate frequency amplifier, a video detector, a video amplifier, a sync separator and the like. Horizontal sync signal .phi.H and vertical sync signal .phi.V separated by receiver 22 are supplied to controller 23 while a video signal is supplied to A/D converter 24. A/D converter 24 converts the analog video signal received and output by receiver 22 into digital video data, and supplies it to RAM 25 or 26. RAMs 25 and 26 each have a 1-field capacity. Such a memory has been described in Japanese Patent Disclosure No. 60-57747. Controller 23 produces various control signals in synchronism with signals .phi.H and .phi.V. More specifically, controller 23 produces address data AD1 and AD2 and supplies them to RAMs 25 and 26, as well as producing read/write signals R/W1 and R/W2, which indicate a write mode when at level "0", and a read mode when at level "1", timing signals .phi.S1, .phi.S2, .phi.n, and .phi.F for driving a liquid-crystal display panel (to be described later), and shift data signal ST. Reference numeral 27 denotes a liquid-crystal display panel which is vertically divided into two portions, as shown in FIG. 1. Segment electrodes of upper liquid-crystal display panel 27A are driven by shift register 28 and segment electrode driver 29, and those of lower liquid-crystal display panel 27B are driven by shift register 30 and segment electrode driver 31. Common electrodes of panel 27A are driven by shift register 32 and common electrode driver 33, and those of panel 27B are driven by shift register 34 and common electrode driver 35. Shift register 28 or 30 receives digital video data from corresponding RAM 25 or 26, and stores it in synchronism with shift clock .phi.S1 or .phi.S2. The digital video data stored in shift registers 28 and 30 are transferred to drivers 29 and 31, respectively, in synchronism with clock .phi.n (FIG. 3(I)) produced for each 2H (H: horizontal scanning period), as shown in FIG. 3(A). Drivers 29 and 31 apply a drive voltage to the segment electrodes of panels 27A and 27B in accordance with frame switching signal .phi.F (FIG. 3(D)) and multi-level voltage VE supplied from a power source (not shown). Shift registers 32 and 34 fetch shift data signal (FIG. 3(G)) produced from controller 23, and shift-drive it in synchronism with clock .phi.n to supply it to drivers 33 and 35, respectively. Thus, drivers 33 and 35 drive the common electrodes of panels 27A and 27B in accordance with the outputs from shift registers 32 and 34, frame switching signal .phi.F, and multi-level voltage VE supplied from a power source (not shown).
A drive method of the conventional liquid-crystal display panel will be described with reference the timing charts of FIGS. 3(A) to 3(K). FIGS. 3(C), 3(E), and 3(K) show the relationships among digital video data E(n-1), E(n), and E(n+1), row addresses of RAM 25, and 1st and 121st common-electrode drive signals X1 and X121 of panels 27A and 27B during each of effective video periods n-1, n, and n+1. Note that n-1, n, and n+1 indicate effective video periods; 1H, 2H, . . . , horizontal scanning periods; E(n-1), E(n), and E(n+1), digital data during effective video periods n-1, n, and n+1; and E(n)1H and E(n+1)121H, digital video data in scanning period 1H during video period n, and digital video data in period 121H during period n+1.
When effective video period n starts, RAM 25 stores digital video data E(n-1) during effective video period n-1. At scanning start timings of periods 1H and 2H during effective video period n, data E(n)1H and E(n)2H are written at addresses 1 and 2 of RAM 26 and, at the same time, data E(n-1)1H and E(n-1)121H during period n-1 are read out from addresses 1 and 121 of RAM 25 to be supplied to shift registers 28 and 30. Data E(n-1)1H and E(n-1)121H during period n-1 are shift-input to shift registers 28 and 30 in synchronism with shift clocks .phi.S1 and .phi.S2, and are read out in response to next clock .phi.n, to be latched by drivers 29 and 31. At timings of periods 3H and 4H during period n, the 1st and 121st common electrodes of panels 27A and 27B are driven for a display operation. Therefore, drive signals X1 and X121 are as shown in FIG. 3(K). More specifically, during period n, data E(n)1H to E(n)240H produced from A/D converter 24 are written at addresses 1 to 240 of RAM 26. At the same time, digital video data during period n-1 stored at addresses 1 to 240 of RAM 25 are read out as a combination of E(n-1)1H and E(n-1)121H, and as a combination of E(n-1)2H and E(n-1)122H,. . . , so that data E(n-1)1H, E(n-1)2H, . . . are supplied to panel 27A, and data E(n-1)121H, E(n-1)122H, . . . are supplied to panel 27B to be displayed thereon. During period n+1, data E(n+1) generated from A/D converter 24 is written in RAM 25, and data E(n) stored in RAM 26 is read out to be displayed.
Frame switching signal .phi.F (FIG. 3(D)) determines the read and write modes of digital video data with respect to of RAMS 25 and 26. When signal .phi.F is at "0" level, "0"-level signal R/W1 is supplied to RAM 25 to write data therein, and "1"-level signal R/W2 is supplied to RAM 26 to read out data therefrom. To the contrary, when signal .phi.F is at "1" level, data is written in RAM 26, and is read out of RAM 25.
As can be understood from the above description, with the drive method of the conventional liquid-crystal display panel, since the 1st and 121st common electrodes are simultaneously selected during horizontal scanning period 2H, the duty ratio becomes 1/2. However, since digital data written in one RAM during the n field is read out during the n+1 field and digital video data is written in the other RAM during the n+1 field, and such an operation is repeated, a total memory capacity of RAMs must correspond to 2 fields. For example, when a single frame is constituted by 240.times.320 pixels and each pixel has 4-bit data, the capacity of the RAMs is required to be (240.times.320.times.4.times.2) bits.